In the semiconductor industry, gate arrays are employed as customized integrated circuit devices. Implementing electrical logic functions, gate arrays realize AND, NAND, OR, and NOR gates, as well as combinations of these gate functions to form latches, flip flops, and adders, for example.
In order to customize specific electrical logic functions on a semiconductor substrate, complementary metal oxide semiconductor ("CMOS") gate arrays typically comprise a base array of a plurality of P type and a plurality of N type transistors. Both P and N type transistors are arranged in columns, enabling customization by intra and inter logical connections. These connections allow electrical current to pass between interconnected transistors. Further, these connectors are usually formed by one or more metal mask layers.
Traditionally, gate arrays are formed on a semiconductor substrate having drain-source diffusion regions. It should be noted that for the purposes of the present invention, source and drain are interchangeable, particularly in light of the physics of field effect transistor ("FET") devices. These drain-source regions are sufficiently spaced apart and insulated from one another to enable the formation of a gate region. As disclosed in U.S. Pat. No. 4,620,270, commonly assigned with the present invention and incorporated herein by reference, by this arrangement, a chain of continuously electrically connected transistors can be formed. The drain of each transistor of the series is thus electrically coupled to the source of an adjacent transistor. As such, logical functions can be realized by electrical coupling selected transistors from the chain.
Once customized, industry practice is to employ some means to increase the level of reliability of the customized IC. As such, positioned between each logically realized element is an isolation transistor. Isolation transistors functional purpose is to isolate each logical element from the IC's remaining components. Comprising a gate, source and drain, the isolation transistors gate is coupled to a voltage source or ground, depending on the transistor type, and thereby made inactive. Thus, for example, if the isolation transistor is an N type, the gate is coupled to ground, while if isolation transistor is a P type, the gate is coupled to V.sub.dd or V.sub.cc.
Referring to FIG. 1, a layout is illustrated of a known logic module or integrated circuit ("IC") having several isolation transistors formed on a semiconductor substrate 10. Substrate 10 comprises two diffusion regions, 50 and 52, to form a chain of N channel and P channel transistors, respectively. Adjacent to both N and P diffusion regions are a first and second bus, 54 and 56. First bus 54, neighboring N diffusion region 50, is directly coupled to ground. In contrast, adjacent to P diffusion region is second bus 56, which is directly coupled to a power supply.
At the center of the logic module are a two sets of two transistors, 60 and 60'. These transistors, 60 and 60', are employed for the purposes of forming the intended logic element, such as a dual inverter for example. As discussed above, this logic element is realized by particular interconnects. The realized logic element also comprises an input and an output interconnect, 58 and 59.
Further, isolation transistors, 62, 63, 64, and 65, of the logic module are provided for the purpose of isolating the logic element from the extraneous effects of neighboring logic elements. To this end, the gates of isolation transistors 62 and 64--which are N channel devices--are coupled to ground bus 54 by means of electrical contacts 67 and 68, respectively. In contrast, the gates of isolation transistors 63 and 65--which are P channel devices--are coupled to power bus 56 by means of electrical contacts 69 and 70, respectively. Electrical contacts, 67-70, are formed by extending a conventional contact from the gate of their respective isolation transistors to the metallization layer bus.
Given this configuration, isolation transistors, 62-65, are permanently disabled. This is achieved by the coupling of the isolation transistors' gates to either ground or power supply. Thus, no signals can pass from neighboring circuits to the logic unit represented by transistors 60 and 60'.
The coupling of isolation transistors, 62-65, to their respective buses, 54 and 56, is achieved by means of a conventional contact, as described above. In standard applications and environments, the potential for the conventional contact to open is within some degree of certainty and has a measurable rate of failure.
Furthermore, it has been observed that in the presence of charged particles, photon energy, or electromagnetic radiation, such as in deep space applications, the reliability of gate arrays employing a traditional CMOS architecture has been suspect. A potential failure mechanism exists specifically in the case of the conventional open contact. Under these circumstances, the bombardment of a semiconductor may cause charged particles to migrate to the isolation transistor gate. Further, if the gate is not coupled to its power bus, the voltage induced may cause the gate to change its gate potential and turn on or become conductive, thereby eliminating the isolation between transistors in the column. Thus, a solution is required to improve the reliability of known gate array architectures in a photon energy, electromagnetic radiation or charged particle environment.